1. Technical Field
This invention relates generally to a method of manufacturing integrated circuit (IC) chips and the IC chips produced thereby. More specifically, the present invention relates to a dual work function complementary metal oxide semiconductor (CMOS) device and a method for producing these devices.
2. Background Art
Presently, integrated circuit chips are manufactured by beginning with a wafer. If desired, these wafers may be grown with a given type of impurity, depending upon whether one desires electron acceptors (p-type impurities) or electron donors (n-type impurities) in the wafer.
One of the first processing steps of the wafer in forming an integrated circuit (IC) chip is the creation of device isolation. Shallow trench isolation areas may be formed by defining areas with a photoresist and reactive ion etching to form the shallow trenches. The shallow trenches are then filled with a nonreactive silicon oxide and planarized by a chemical mechanical polish. In some cases, a nitride liner, conventionally a silicon nitride, may be deposited before the oxide, so as to prevent oxidation of the surrounding areas.
Wells are then implanted in the wafer of either or both of the impurities. For example, if one begins with a p-type wafer, n-wells would be implanted. The gate oxide is grown and the various layers of the gate are deposited. A resist is then applied and the gate defined by the standard reactive ion etch method. Another resist layer is used to define the p-extensions, a lightly doped drain is formed, and the resist is removed. The same process is used to form the n-type lightly doped drain regions. The sidewall oxide or spacer is then applied and the source/drain implantation is performed. The space between the gates is then filled and the surface planarized. The aspect ratio of these gates is optimized to approach a value of 1, so that the thinner the gate layers are, the more easily filled the areas between them, the more reliable the metallization process and, hence, the more reliable the chips.
Each set of a gate, a source, a drain and a well forms a field effect transistor (FET). If the source and drain are N+, the FET is known as an NFET and, conversely, if the source and drain are P+, the FET is known as a PFET. In a single work function CMOS device, the gate is doped with a single impurity type. In a dual work function CMOS device, both NFET and PFET devices have their gate dopants tailored in order to achieve an enhanced p-channel device characteristic. This means that each time an area must be implanted with an n-type impurity, the areas that are free of impurities and the areas which are going to be doped with p-type impurities must be protected and vice versa. This leads to a multiplication of the alignment problems involved with each resist patterning step and increased throughput time because of the additional definition steps and two separate implantation steps.
This technique also suffers from limitations inherent in the conventional implantation method. Ion implantation may give rise to dislocations. The generation of dislocations provide paths for leakage of charge out of the wells that store charge in DRAM cells and across junctions. For example, normal VLSI processing conditions usually requires a high dose ion implant, such as the BF.sub.2 ion implant used for p-channel source-drain (S/D) doping (in 0.5 micron technology). This may cause the formation of extended loop dislocations. Should dislocations occur, the chip fails, therefore, it is desirable to prevent the formation of these dislocations.